The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention relates to reducing leakage power in an integrated circuit (IC) device using an external agent.
Power consumption, both dynamic and leakage, is one of the major concerns of IC design. In particular, leakage power may be growing with each successive design generation. One popular power saving technique implemented in notebook computers is to use ICs that can operate in a state or mode of reduced work capability that leads to reduced power consumption.
Some processors can operate according to an internal core clock signal that can be on/off modulated. This is an example of processor clock “throttling” which temporarily puts the processor in a non-active mode, which, in turn significantly reduces processor power consumption. A broader set of power states or work capability modes have been defined to place the processor in various sleep states. In a sleep state, some or all of the computing and I/O functions of the processor are essentially shut down.
However, current designs generally place their I/Os on a separate voltage plane and leave them powered up at all times. The present disclosure addresses this and other issues in reducing idle leakage power to these I/Os that are powered up at all times.